The present invention relates generally to oscillators and more specifically to a CMOS negative resistance oscillator.
The use of integrated circuit technology to reduce power consumption using CMOS devices is well-known in the art. These circuits have generally been CMOS implementations of transistor oscillator circuits. A typical example of the prior art CMOS circuits having low power consumption and high stability is shown in U.S. Pat. No. 4,013,979. This patent shows a "Pierce" circuit wherein the frequency determining network is a crystal in a high impedance .pi. network. Oscillation is initiated by leakage current through two parallel CMOS current path wherein the geometry of the CMOS are unbalanced.
The use of a high impedance .pi. configuration is undesirable in that it requires a greater number of linear components of significant size than, for example, the low impedance series resonance networks. Also, the circuit of the aforementioned patent has steady state operating conditions established by one MOS device, the linear components and the power supply voltage. Thus the oscillator is sensitive to the aging of the linear components as well as fluctuation or variation in the power supply voltage. These effects are undesirable. Similarly, the high impedance network is not as easy to temperature stabilize as the low impedance series mode of operation.
Thus there exists a need for a CMOS oscillator which reduces the number of linear components, has the frequency determining network operated in the series resonance mode, and whose steady state operating conditions are idependent of the frequency determining network and insensitive to power supply voltage variation.